Search - fpga ddr

[Other resource] DDR_SDRAM_Controller

Description: DDR RAM控制器的VHDL源码，实现平台是Lattice FPGA，功能验证通过-DDR RAM controller VHDL source code, achieving the platform of Lattice FPGA, functional verification through
Platform: | Size: 678583 | Author: 钟方 | Hits:

[Other resource] xapp858[1]

Description: XAPP858 - 利用 Virtex-5 FPGA 实现的高性能 DDR2 SDRAM 接口数据采集本应用指南描述了用于实现 667 Mbps（333 MHz）高性能 DDR2 SDRAM 接口的控制器和数据采集的技巧。本数据采集技巧使用了输入串行器/解串器（ISERDES）和输出串行器/解串器（OSERDES）的功能。-XAPP858-use Virtex-5 FPGA high-performance DDR2 SDRA M Interface Data Acquisition Guide describes the application for achieving 667 Mbps (333 MHz) high-performance DDR 2 SDRAM Interface controller and data acquisition techniques. The data collection techniques used serial input / Solution Series (ISERDES) and serial output / Solution Series (O Legacy) function.
Platform: | Size: 297475 | Author: mingming | Hits:

[Other resource] ddr_ctrl

Description: verilog hdl coding DDR sdram control for fpga
Platform: | Size: 27946 | Author: 王郁 | Hits:

[Embeded-SCM Develop] DDRinterface

Description: 《ALTERA FPGA/CPLD高级篇》高速DDR存储器数据接口设计实例
Platform: | Size: 25327 | Author: shicheng342 | Hits:

[Other resource] DDRSDRAM

Description: 基于FPGA 实现DDR SDRAM的控制器
Platform: | Size: 474402 | Author: 张宁 | Hits:

[Other] FPGADDR

Description: 基于FPGA的DDR接口驱动上电初始化的部分已经完成主要的功能部分尚未编写
Platform: | Size: 7770 | Author: sunshine | Hits:

[Other resource] rtl

Description: DDR控制器已通过FPGA 验证大家不要错过哦
Platform: | Size: 52506 | Author: kin | Hits:

[Other resource] ddr_reader

Description: xilinx fpga 的 micoblaze 下的 ddr ram 读程序
Platform: | Size: 1966 | Author: zeng | Hits:

[SCM] upload_code

Description: 每个代码见压缩包内文件名，分别为使用单片机控制AD9627的代码，已在硬件电路实现；基于FPGA的DDR SDRAM控制源代码，将文件夹内文件加入同一工程即可；以及三份FPGA内部学习资料。 C代码开发环境为KeilC，verilog代码开发环境为Quartus。 -See each code within the compressed package file name, respectively, for the use of the AD9627 single-chip control of code, has been in the hardware circuit FPGA-based DDR SDRAM control source code, will be adding a document folder to the same project and three FPGA internal learning materials. C code development environment for KeilC, verilog code development environment for the Quartus.
Platform: | Size: 1746944 | Author: 姜琰俊 | Hits:

[VHDL-FPGA-Verilog] mictor20110113

Description: ddr控制参考代码,串口通信可以基于此进行二次开发,fpga参考设计，对ddr设计开发有一定的帮助-ddr controller ref code
Platform: | Size: 986112 | Author: wangqijun | Hits:

[VHDL-FPGA-Verilog] ug230.pdf

Description: The Spartan-3E Starter Kit board highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications. The board highlights these features: • Spartan-3E FPGA specific features • Parallel NOR Flash configuration • MultiBoot FPGA configuration from Parallel NOR Flash PROM • SPI serial Flash configuration • Embedded development • MicroBlazeTM 32-bit embedded RISC processor • PicoBlazeTM 8-bit embedded controller • DDR memory interfaces
Platform: | Size: 5851136 | Author: Akalu Lentiro | Hits:

[VHDL-FPGA-Verilog] ddr_verilog

Description: verilog HDL语言实现在FPGA上控制DDR的逻辑，方法简单易懂，适合新手参考-Verilog HDL language on FPGA control DDR logical, simple to understand for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] ddr_kongzhiqi

Description: fpga上用verilog HDL实现的ddr控制器，简单易懂，适合新手参考-FPGA on the use the verilog HDL implementation of the DDR controller, easy to understand, suitable for novice reference
Platform: | Size: 18432 | Author: fan | Hits:

[VHDL-FPGA-Verilog] DDRSDRAM_

Description: 基于FPGA 的DDR SDRAM 的重要资料内附代码-FPGA-based DDR SDRAM code containing important information
Platform: | Size: 481280 | Author: 毕禹昕 | Hits:

[Other Embeded program] TimeOutCounter

Description: 用于FPGA内部计数辅助DDR操作，便于开发-TimeOut Counter
Platform: | Size: 1024 | Author: wang | Hits:

[VHDL-FPGA-Verilog] DDRController

Description: DDR3控制器，用于FPGA内部对DDR进行操作，利用Avlone总线进行对接-DDR controller
Platform: | Size: 7168 | Author: wang | Hits:

[Software Engineering] audio

Description: 一个关于音频播放的fpga驱动代码。流程是从sd卡中读取音频文件，然后缓存到DDR中，再通过一定的时序关系让音频WM8731芯片播放-An audio playback on fpga driver code. The process is to read audio files from sd card and then cached to DDR, and then through a certain timing relationships allow playback of audio WM8731 chip
Platform: | Size: 215040 | Author: lilianghua | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list